IR1176STR【PDF 3/12 页】IC DRIVER RECT SYNC 5V 4A 20SSOP

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IR1176

Dynamic Electrical Characteristics

Vdd=5V, T A = 25 o C, Rbias = 34.0K unless otherwise specified.

Symbol

Vdd

Iqdd

Freq

UVSET+

UVSET-

Vxth+

Vxth-

Tadv

Td

Isink

Definition

Supply voltage operating range

Vdd quiescent current (x1 = x2 = 0V or 5V, Iout = 0)

Operating frequency

UVSET positive going threshold

UVSET negative going threshold

X1/X2 Input positive going threshold

X1/X2 Input negative going threshold

Externally adjustable lead time (advance)

Externally adjustable dead-time for Q1 and Q2

Q1,Q2 output sink current (Vdd=5.0V,

Min.

4.0

—

100

1.10

0.8

—

—

—

20

—

Typ.

—

4

—

—

—

1.4

1.0

—

—

4

Max.

5.25

5

2000

1.4

1.1

—

—

500

—

—

Units

V DC

A

KHz

V

V

V DC

V DC

nsec

nsec

(peak)

pulsed, 10 usec)

Isource

Q1,Q2 output source current (Vdd=5.0V,

—

4

—

A

(peak)

pulsed, 10 usec)

VOH

VOL

tio

Q1, Q2 High level voltage (Iout = 20mA)

Q1, Q2 Low level voltage (Iout = 20mA)

Input to output delay (PLL bypassed, cross coupled

—

—

—

Vdd- 0.20

0.10

20

—

—

—

V

nsec

mode)

tr

tf

Vtr

Gate turn-on rise time (C1=1000pf, Vdd=5V)

Gate turn-off fall time (C1=1000pf, Vdd=5V)

Cross-over voltage (Vdd=5Vdc, DTIN shorted to

—

—

—

20

20

2.5

—

—

—

nsec

nsec

V DC

DTOUT, C1=1000pf) Fig. 3

Rbias

Vbias

Tjitter

Ichgpump

Vchgpump

Kvco_dc

Required bias resistor (1%)

Voltage at Rbias pin

Phase-lock loop output jitter

Charge pump output current (at VFLTR pin)

Charge pump output voltage (at VFLTR pin)

PLL Vco DC gain (per design)

—

—

-20

—

1.3

—

34.0

1.25

—

50

1.5

62

—

—

20

—

1.7

—

K ?

V DC

nsec

μ A DC

V DC

KHz/

Volt

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